The specific ON-resistance and the blocking voltage in semiconductor power devices are subject to a trade-off relation determined by the bandgap of the material used in the substrate. One effective method for attaining better performance than power devices containing silicon is to use a substrate material whose bandgap is larger than silicon. Silicon carbide (SiC) is the special focus of much attention as a substrate material because of features such as a satisfactorily wide bandgap approximately three times larger than silicon, easily formable p-type and n-type conductance regions, and oxidized film formed by thermal oxidation. These SiC features offer new possibilities for devices including high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices.
Among the various power devices, vertical power MOSFET are utilized in a wide range of areas because of their excellent switching characteristics. Vertical power MOSFET devices are broadly grouped into two types: DMOSFET and UMOSFET. The DMOSFET (depletion MOSFET) is a simple structure with the channels formed on the substrate surface and so is comparatively easy to produce and has an effective blocking voltage however it has the drawbacks of a large cell pitch and large channel resistance. The UMOSFET on the other hand is a comparatively complex structure with the channels formed on the trench side wall and features such as a small cell pitch and a small channel resistance. Because of these features, there is growing trend to shift from DMOSFET to UMOSFET.
However use of silicon carbide UMOSFET reveals the serious problem that channel mobility is extremely small. Causes of small channel mobility include the forming of an interface state where carbon remains on the boundary where the silicon carbide was thermal-oxidized, and a loss of sliding effect on trench side wall surfaces formed by dry etching. Both of these causes differ greatly compared to use of silicon material. When the interface state becomes larger, coulomb scattering increases due to charges trapped on the boundary, and when the trench side wall surface is no longer slippery then scattering increases due to interface (boundary) roughness. These conditions cause a drastic drop in channel mobility.
Modifying the manufacturing process can render improvements to a certain extent but attaining improvements on the same level as silicon is impossible. Attaining the same improvement level is difficult because completely removing carbon from the boundary is impossible since there is carbon within the substrate, as well as the fact that physical properties are greatly different from silicon in that silicon carbide is extremely hard and difficult to machine, and moreover does not easily re-crystallize.
If channel mobility is low then other measures can be utilized to reduce channel resistance. Such measures may for example include shortening the channel length, or reducing the density of the p body region forming the channels in order to lower the threshold voltage. However, shortening the channel length shortens the distance between the drift layer and the source region so that punch-through tends to easily occur in the OFF state and the blocking voltage drops. Moreover, lowering the p body region concentration tends to extend the depletion layer within the p body region during the OFF state so that the same drop in blocking voltage occurs.
However one method for lowering the threshold voltage without causing a drop in blocking voltage is known that utilizes a structure in which only the trench side wall vicinity in the p body regions is set to a low concentration. The threshold voltage can be lowered without a drop in blocking voltage by lowering the concentration only around the oxidized film boundary that affects the threshold voltage. Methods for forming this structure include a method that lowers the P density on the surface by ion implantation of n-type impurities, and a method for forming n-type impurities by epitaxial growth towards the trench side wall. The former method damages the channels due to ion implantation so that not only is there a drop in mobility but also a possible deterioration in oxidized film reliability. The latter method required in-process epitaxial growth, yet forming an epitaxial layer on a surface roughened by dry etching is difficult and also has many problems in terms of cost and technical issues.
A technology describing a double-gate DMOSFET with structure resistant to punch-through between the source region and drift layer is disclosed in Japanese Patent No. 3319215. This structure as shown in FIG. 1 is a channel extending horizontally in parallel with the substrate surface and enclosed from above and below by two gates. The lower gate acts to prevent an electrical field from forming on the channel and in this way helps resist punch-through between the source region and drift layer. However, since the channels in this structure extend laterally, the cell pitch is wide so the cell integration is not dense enough and consequently the specific ON-resistance cannot be lowered sufficiently. Another problem is that the lower gate electrode must be embedded creating a more costly production process. Moreover this document gives no description whatsoever of the interrelation of p body dimension, p body width and dopant concentration.
Though the structure is different from a power MOSFET, the technology disclosed in JP-A-Hei05 (1993)-110091 describes a double-gate structure TFT (Thin Film Transistor) with a 2000 (0.2 μm) angstrom gap between the gate electrodes as a structure resistant to punch-through between the source and drain and that allows higher current flow. In this double-gate TFT with thin channels, the total channel region is inverted, a large ON current can be obtained and there is no increase in OFF current even in short channels (paragraphs 0006-7, paragraph 0017, see FIG. 1). However this document discloses no technology relating to vertical power MOSFET, and also gives no description of the relation between the body region enclosed by trenches formed on both sides of the channel forming regions in the UMOSFET, the width of the body region enclosed by the trenches, and the dopant concentration, etc.